1. Field of the Invention
The invention relates to the field of semiconductor memory devices employing floating gates and the processes and methods for fabricating these devices.
2. Prior Art
One class of non-volatile semiconductor memories employs floating gates, that is, gates which are completely surrounded by an insulative layer such as silicon dioxide. Typically, a polycrystalline silicon (polysilicon layer is used to form floating gates. These gates are electrically charged, most often with electrons by transferring charge into and from the gates through a variety of mechanisms. The presence or absence of this charge represents stored, binary information. An early example of such a device is shown in U.S. Pat. No. 3,500,142.
The earliest commercial electrically programmable readonly memories (EPROMs) employing floating gates used p-channel devices which are programmed through avalanche injection. Charge is removed from these devices by exposing the array to electromagnetic radiation such as ultraviolet light (See U.S. Pat. No. 3,660,819). Later, EPROMs used n-channel devices and relied on channel injection as the mechanism for transferring charge into the floating gates (See U.S. Pat. No. 3,984,822). Many EPROMs fabricated with current technology still rely on channel injection for transferring charge into the floating gates and radiation for erasing the gates.
Another category of semiconductor floating gate memory devices are both electrically programmable and electrically erasable. Such a device is shown in U.S. Pat. No. 4,203,158. Tunneling is used through a thin oxide region for transferring charge into and from the floating gates. Such memories are commercially available such as the Intel 2816. In these memories, two devices are required for each memory cell. One device includes the floating gate and the other (typcially an ordinary field-effect transistor) is used to isolate the floating gate device during various memory cycles.
A more recent category of floating gate memory devices uses channel injection for charging floating gates and tunneling for removing charge from the gates. Here, each memory cell comprises only a single device and the entire memory array is erased at one time, that is, individual cells or groups of cells are not separately erasable as in current EEPROMs. These memories are sometimes referred to as "flash" EPROMs or EEPROMs. An example of these devices is disclosed in pending application Ser. No. 892,446, filed Aug. 4, 1986, entitled "Low Voltage EEPROM Cell" which application is assigned to the assignee of the present application. The devices described in this copending application use asymmetrical source/drain regions.
In some cases, the floating gate memory devices are fabricated in arrays where each device or device pair is separated from other devices by field oxide regions. An example of this is shown in U.S. Pat. No. 4,114,255. In these arrays, a metal contact is needed for each device or device-pair, these metal contacts limit the reduction of device area. Another problem associated with fabricating cells of the type described in the above-mentioned patent application is described in conjunction with FIG. 1 of this application.
Other arrays substantially reduce the metal contacts needed by using elongated source/drain regions which are disposed beneath oxide regions. These arrays sometimes referred to as having "buried bit lines" or using "contactless cells" requires virtual ground circuitry for sensing and programming. An example of this type of array is shown in U.S. Pat. No. 4,267,632 with virtual ground circuitry being shown in U.S. Pat. No. 4,460,981. Other examples of memories employing this technology are shown in U.S. Pat. Nos. 4,112,509; 4,148,207; 4,151,021; 4,282,446; 4,373,248; 4,493,057; and 4,503,524. This technology is also described in Electronics "Contactless Arrays for EPROMS Arrive Just in Time", Nov. 27, 1986, beginning at page 70; IEDM 86 "High Density Contactless Self-Aligned EPROM Cell Array Technology", beginning at page 592; and ISSCC 87, Section VII: Non-Volatile Memory, "A 1 Mb CMOS EPROM with a 13.5 m2 cell".
As will be seen, the present invention provides an electrically erasable and programmable cell of the variety referred to as the contactless cell.